1. Field of the Invention
The present invention relates to a spread spectrum clock generator and a method of generating a spread spectrum clock.
2. Description of the Related Art
A clock generator, such as 10 in FIG. 1, generally comprises a clock source 100 and a phase-locked loop (PLL) 102. This generator 10 generates a system clock usually having square waves and a 50% duty cycle. The system clock is then used in many different types of systems, such as a memory system including a memory module 14 and a memory controller 12.
System clocks such as this can be a source of unwanted electromagnetic interference (EMI). EMI can cause problems in electronic circuits, as it interferes with signal transmission. As technology improves, circuits can operate faster, requiring faster clocks that in turn generate more EMI. One technique to alleviate EMI is to use spread spectrum clock generators (SSCG). These clocks are referred to as spread spectrum in that their frequency is spread out over different frequencies, avoiding the energy peaks at clock edges. In some instances, SSCGs are implemented using PLLs as shown in the US patents described below. PLLs vary the voltage to a voltage controlled oscillator (VCO), causing varying delays in the clock.
Examples of this approach are shown in U.S. Pat. No. 5,631,920, issued May 20, 1997; U.S. Pat. No. 6,292,507 issued Sep. 18, 2001; and U.S. Pat. No. 6,351,485, issued Feb. 26, 2002. The use of a PLL typically allows a clock cycle to be switched between two frequency limits, adjusting the clock frequency back and forth between them. This approach may be somewhat limited, as it only allows for two fixed frequencies to be used, and does not allow programmable control.
Another approach is shown in U.S. Pat. No. 6,501,307, issued Dec. 31, 2002. As shown in FIG. 2, this approach has 2 capacitors used as loads switched by counter-sequencer 20, clocked by fixed clock FCLK. The counter-sequencer 20 drives first control signal CTL1 to the gate of load-switching transistor 22, and second control signal CTL2 to the gate of second load-switching transistor 24. When CTL1 is high, capacitor 26 has to be charged and discharged by input buffer 28 before the logic threshold of output buffer 30 is reached, thus delaying the clock edges. When CTL2 is high, capacitor 32 has to be charged and discharged by input buffer 28 before the logic threshold of output buffer 30 is reached, thus also delaying the clock edges. When both CTL1 and CTL2 are high, both capacitors have to be charged, further delaying the clock edges. However, these loads cannot be changed linearly to adjust the clock frequency as needed.